The present invention relates, generally, to input buffers. More particularly, the present invention relates to an input buffer and method configured for voltage level detection that can facilitate detection and use of multiple levels of voltage for operation, such as for testing purposes, as well as provide for multiple operations from the same input pad.
Input buffers have been long used in various analog and digital applications. While many input buffers are optimized for AC switching techniques and applications, other input buffers are configured for optimizing voltage detection. Through use of input buffers configured as voltage detectors, a determination can be made whether to initiate or cease a particular system function. Such voltage detectors are often configured to detect the level of the supply voltage (VCC) of integrated circuits, including the detection of specified ranges for which an integrated circuit is designed, prohibiting operation of the integrated circuit if the level of voltage is outside the specified range, or determining whether a threshold level has been reached before permitting operation of a particular application within the integrated circuit.
In general, input buffers configured as voltage detectors are configured to operate for only one threshold level, i.e., trip for only one point, to confirm whether the voltage level is above or below the threshold level. For example, in microprocessor-based applications, an input buffer configured as a source voltage detector can be utilized to detect the voltage level of the power supply voltage within the memory modules of the microprocessor-based system. Through this detection process that determines whether a threshold level has been reached, the voltage detector can initiate signals to control devices to operate the power supply voltage for the memory blocks of the microprocessor-based system.
Many integrated circuit applications are designed with voltage detectors configured for detecting operation at a high voltage, a xe2x80x9csuper voltagexe2x80x9d or xe2x80x9cSVxe2x80x9d level. This SV level, which is configured internally within the chip, is generally for use only by circuit manufacturers and is set above normal operating conditions to suitably test the die, i.e., to place the die in different testing conditions, and is not typically utilized by consumers of the integrated circuits. While such SV levels were originally designed for between 9 volts to 12 volts, improvements and changes to the various technologies and processes has resulted in the lowering of the SV levels to 7 volts or less to prevent breaking down from the active area to the substrate on the die, and thus moved the SV levels closer to the operating range of integrated circuits. Such developments in the SV levels have resulted in limited margins of operation for such testing applications.
In addition to a reduction of the SV levels, circuit designers have required modern integrated circuits (ICs) to be configured with a minimal number of pins to simplify the input/output connection system of the integrated circuits. Moreover, input buffers configured as voltage detectors, which are more commonly comprised of CMOS-based logic devices, are generally designed to provide for two states of operation, i.e., the input buffer is configured to accept high or low voltage signals from external sources and then provide a logic state to the integrated circuit corresponding to the high or low signals. For example, the voltage detectors are typically configured to work from one point, and to detect a voltage level when it is in a xe2x80x9chighxe2x80x9d condition, i.e., greater than a threshold voltage, and in a xe2x80x9clowxe2x80x9d condition, i.e., lower than a threshold voltage. Further, modern voltage detectors are configured to operate in either xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d, or in the transition in between, but not in the midrange, i.e., in between xe2x80x9chighxe2x80x9d or xe2x80x9clow.xe2x80x9d
With reference to FIG. 1, a prior art input buffer 100 configured for voltage detection is illustrated. Input buffer 100 comprises a differential amplifier including two input terminals, e.g. the gates of transistors M3 and M4, coupled to an input signal INPUT and a reference signal REF, and having an output signal OUT_DIFF provided from the output of a series of succeeding or cascading inverter stages 102, 104 and 106. Input buffer 100 is configured to amplify the difference between the input signal INPUT and the reference signal REF into a high or low signal.
For example, with reference to FIG. 2, during operation, when input signal INPUT is at zero or ground, e.g., the output of transistor M2 is zero, the inverted output signal OUT_DIFF will remain as a high signal; when input signal INPUT goes above the reference signal REF, the output signal OUT_DIFF will switch to a low signal; and when input signal INPUT again goes below the reference signal REF, the output signal OUT_DIFF will switch again to a high signal. Thus, only two states of operation are realized, high and low, i.e., input buffer 100 recognizes a high or low state, but not any other states in between the two states.
As a result of being limited to two states of operation, the functions of an IC using such an input buffer 100 are also somewhat restricted. For example, in an IC that has two command pins A and B, with two states that can be realized for each, has only four functions or commands can be decoded, i.e., for A,B=0,0; A,B=0,1; A,B=1,0; A,B=1,1. Although increasing the number of pins can increase the number of functions available, with the trend towards smaller packages, it is difficult and adds complexity and cost to the overall design and manufacturing of the IC to implement additional control pins to packages.
Therefore, a need exists for an improved input buffer configured for voltage detection that can facilitate use of a mid-level voltage for testing purposes, as well as provide for multiple operations from the same input pad.
The present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, an improved input buffer and method configured for voltage detection system are provided that can facilitate detection of a multiple levels of voltage, such as a mid-level voltage that may be used for testing purposes. In accordance with an exemplary embodiment, an exemplary input buffer circuit configured for voltage detection comprises a reference generator and a multi-state voltage detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. In accordance with an exemplary embodiment, the multi-state detector comprises a three-state detector. The three-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to at least two reference voltages, provide output signals to at least three output terminals representing a high, low and mid-level state of operation. In accordance with an exemplary embodiment, the three-state detector comprises two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements.
In accordance with another aspect of the present invention, an exemplary input buffer circuit can facilitate multiple operations from the same input pad. For example, through use of a three-state detector, at least three states of operation can be realized. Thus, in accordance with an exemplary embodiment in which three states of operation are realized, up to eight decoded states can be obtained. As a result, additional functions can be provided by the three-state detector without requiring the addition of command pins to the IC design. Moreover, through the detection of additional levels of voltage besides the detection of a mid-level voltage range, even more functions can be provided without adding command pins.